Many integrated circuits (ICs), such as application specific integrated circuits (ASICs), contain a number of modules. For example, an integrated circuit may include a memory, a central processing unit (CPU) and one or more peripheral modules.
In a simple IC, the operations are usually clocked by a single clock signal, and thus the modules run at the same frequency. Such a system is termed a synchronous system. In a synchronous system, clock bridges and buffers between modules are not usually required for transmitting data from one module to the other.
In more complicated synchronous systems, a very large clock tree is required to distribute the clock signal throughout the entire system. The clock tree distributes the clock signal(s) from a common point to all the elements that need it. As the size of the clock tree increases, it can become difficult to balance the clock tree to provide phase synchronicity between branches of the clock tree. In addition, a large clock tree consumes a lot of power.
In some ICs, different modules are clocked at different clock speeds. In these systems, each module is clocked by its own clock, so there is no need to route a global clock tree between modules. This allows each clock to be at the optimum speed for that module. These systems are termed a globally asynchronous locally synchronous (GALS) systems, and the usage of these systems is increasing. Each module or set of modules that utilise a common single clock belong to a single domain. The use of different clocks in different domains allows independent dynamic voltage scaling in those domains.
In addition, leakage current of sub-micron IC technology has increased. Thus, it is desirable to implement physical separation between modules to allow independent voltage and frequency scaling. As the number of transistors is ICs is increasing, the number of domains is also increasing. As a result of this, efficient data transfer across the domain boundaries is becoming increasingly important. The ability to provide fully asynchronous and independent domains on an IC is also becoming increasingly important.
Communication between the domains is typically performed on dedicated channels. Thus each domain is provided with a channel for each of the other domains with which it communicates. The component that handles communication across each domain boundary can be termed a clock boundary.
One commonly employed technique for transferring data over a domain boundary, where the domains are clock domains, is signal synchronizing. A synchroniser is used with some or all data signals on the communication channel, to ensure that the signal is aligned or phase-shifted to the clock on the destination domain. Metastability is an important issue in asynchronous circuits, and the synchroniser can minimises the probability of a metastable state being entered into.
One way of using synchronisers to transfer data is termed the hand-shaking protocol. In one example, when new information is available for transmission, a control signal is transmitted to a destination domain via a synchroniser indicating that there is new information. The destination domain reads this information, and sends a control signal back via a synchroniser, indicating that this information has been read. This indicates to the transmission side that new data can be prepared for transmission. Synchronising both signals means that metastability problems can be avoided, however transmission of data can be slow.
Since a dedicated channel is provided between components, a response must be waited for before a new request can be transmitted. Thus, the operation latency can also delay the signals. Typically, for efficient operation burst operation is used for transmission of data. In burst mode, the transmitter transmits data repeatedly without waiting for a response or waiting for an internal process to terminate before continuing the transfer of data.
Other components that have been used in addition to synchronisers to control data transfer in an integrated circuit are buffers such as First In-First Out (FIFO) components. FIFOs have been used to hold data temporarily while waiting for a suitable control signal.
The present invention seeks to provide improvements in transferring data over a border separating domains which may have different clock frequencies and/or clock phases.